Senior SoC Verification Engineer - SystemVerilog​/UVM

A leading semiconductor company in California is seeking a Design Verification Engineer to join a high-performance design team. The role involves developing verification environments, designing verification components, and analyzing simulation failures. Candidates should have over 12 years of experience and a Bachelor’s degree in a relevant field. Strong knowledge of System Verilog and UVM is required. This position offers a competitive salary and benefits.
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