Lead ASIC Verification Engineer; SystemVerilog/UVM
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-01-12
Listing for:
Broadcom
Full Time
position Listed on 2026-01-12
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer, Test Engineer, Software Engineer
Job Description & How to Apply Below
A leading semiconductor company in San Jose, California is looking for an experienced ASIC Verification Engineer. This role demands a minimum of 10 years in developing complex Verification Environments and a proficient understanding of System Verilog and Verification Methodologies. Candidates should have experience with PCI Express and leadership abilities to mentor junior engineers. The company offers a competitive salary range of $141,300 to $226,000 along with comprehensive benefits, including medical, dental, and 401(K) plans.
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