SoC Verification Engineer – UVM/SystemVerilog; Equity
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-01-12
Listing for:
Broadcom Inc.
Full Time
position Listed on 2026-01-12
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Engineering Design & Technologists, Test Engineer
Job Description & How to Apply Below
A leading semiconductor company in California is seeking a Design Verification Engineer to join a high-performance design team. The role involves developing verification environments, designing verification components, and analyzing simulation failures. Candidates should have over 12 years of experience and a Bachelor’s degree in a relevant field. Strong knowledge of System Verilog and UVM is required. Competitive salary and benefits offered.
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