Senior ASIC Digital Design Engineer

Direct message the job poster from Lumicity

Located on-site in San Jose, CA

This is an exciting opportunity to work on high-speed digital integrated circuits for a startup that has groundbreaking technology and has raised over $100 million in funding. You will be working on RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the company’s next generation products.

• Contribute to RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for next generation products.
• Collaborate with hardware and software teams to ensure design integrity across the ASIC flow.

• B.S. or M.S. in Electrical Engineering, Computer Engineering or similar
• Experience with Hardware Description Languages such as Verilog or System Verilog
• Strong background in Digital ASIC Design with understanding of the complete ASIC design flow from specification to tape-out
• Experience with Cadence or Synopsys EDA tools such as Tempus, Prime Time, Genus, Design Compiler, Formality or Jasper Gold
• Scripting experience with Python, TCL or Perl
• Experience in Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain

• Working with protocols for Optical Communications
• Digital Data Communication techniques including scrambling or forward error correction (FEC)

• 401K
• Bonus
• Stock/Equity
• Full Premium Healthcare

• Mid-Senior level

• Full-time

• Semiconductor Manufacturing