Senior Chip-Level Verification Engineer; SystemVerilog/UVM
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-03-08
Listing for:
Sivaltech
Full Time
position Listed on 2026-03-08
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Software Engineer, Test Engineer
Job Description & How to Apply Below
A technology firm in San Francisco is seeking a skilled Design Verification Engineer with expertise in System Verilog and UVM methodologies. The ideal candidate will develop and debug verification test benches, integrate various components, and collaborate with design engineers. Strong problem-solving and communication skills are essential. An education in Electrical or Computer Engineering is required. Interested applicants should send their resumes to the provided email.
#J-18808-Ljbffr
Position Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×