Substrate Layout Engineer

The Signal-Integrity & Packaging (SIP) team manages the external electrical interfaces of Annapurna Lab's chip devices, focusing on signal integrity, power integrity, and electrical usage.

The team collaborates with the Back End team to integrate interfaces into the die, designs package layouts for BGA substrates, and conducts signal and power integrity simulations. The team partners with the system team to develop optimal pin‑out and PCB breakout schemes, performs electrical characterization of interfaces, and develops software tools for debug and diagnostics.

As a SIP team member, the scope of your work will be focused on package substrate layout, with a blend of signal and power‑integrity extractions and simulations, as well as influencing the DIE I/O structures.

• Design and layout of large and complex package substrates.
• Understanding package substrate technologies and layout design rules.
• Proficiency in signal and power‑integrity considerations.
• Layout test studies of die bump‑out structures and package substrate breakout.
• Layout test studies of package pin‑out arrangements and PCB board implementation.
• Continuously improve the package design work by initiating initiatives that drive efficiency, and in turn improve quality, cost, and schedule of the package layout work.

The position is for an entry level, and we will teach and mentor all aspects of the role. No prior hands‑on experience in the above list is required.

• BSc in Electrical Engineering, fresh graduate to 2 years work experience.
• General background in modern digital interfaces (e.g. PCI, DRAM).

• Bachelor's degree in computer science or equivalent.
• Background in PCB layout, even as hobbyist.
• Attention to small details, striving for accurate and high‑quality deliverables.

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