Static Timing Analysis; STA Engineer

Position: Static Timing Analysis (STA) Engineer
Job Title:
Static Timing Analysis (STA) Engineer

Location:
Bay Area, CA

Duration:
Full time

Job Overview:

We are seeking a Static Timing Analysis (STA) Engineer to contribute to the timing verification and closure of high-performance ASICs, SoCs, and custom semiconductor designs.
The ideal candidate will be responsible for performing timing analysis, debugging violations, optimizing designs for performance, and working closely with physical design and RTL teams to achieve sign-off methodologies, and hands-on-experience with EDA tools such as Synopsys Prime Time, Cadence Tempus, or equivalent tools.

Key Responsibilities:

Timing Analysis & Closure:

• Perform full-chip static timing analysis (STA) at block and top level across multiple process, voltage, and temperature (PVT) corners.

• Debug setup, hold, clock skew, transition time, and noise violations to meet timing closure targets.

• Analyze and resolve cross-talk, signal integrity, and OCV (On-Chip Variation) effects.

• Perform clock domain crossing (CDC) analysis and ensure proper constraints definition.

Constraint Development & Optimization:

• Develop and validate timing constraints SDC
for multi-mode, multi-corner analysis.

• Collaborate with RTL and physical design teams to optimize constraints and resolve timing issues.

• Optimize clocking strategies, path balancing, and skew reduction for improved performance.

Sign-Off & Automation:

work on sign-off timing verification using industry-standard EDA tools (Synopsys Prime Time, Cadence Tempus, ANSYS Red Hawk for power-aware timing).

• Automate STA processes using scripting in Tcl, Perl, or Python to improve efficiency.

• Generate detailed timing reports and sign-off documentation.

Required

Skills & Experience:



• 7+ years of experience in Static Timing Analysis (STA) and sign-off for ASIC or SoC designs.

• Proficieney in STA tools such as Synopsys Prime Time, Cadence Tempus. or equivalent.

• Strong understanding of timing closure metodologies, PVT variations, and OCV effects.

• Hands-on experience with constraint development (SDC), clock tree analysis, and optimization.

• Knowledge of low-power design techniques, multi-clock domain handling, and CDC checks.

• Proficiency in scripting languages (Tcl, Peri, Python) for STA automation.

Strong debugging and problem-solving skills with an ability to work in cross-functions teams.