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Principal Power Engineer -Datacenter Systems

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: Acceler8 Talent
Full Time position
Listed on 2026-03-01
Job specializations:
  • Engineering
    Electrical Engineering, Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below

Acceler8 Talent is partnering with a well-funded AI chip startup (>$130m Series A), backed by world-class investors, to hire an experienced Power Engineer
.

This team is building a rack-scale AI data center platform purpose-built for next-generation GenAI workloads. Led by senior engineers with deep experience at Google delivering large-scale, high-performance infrastructure, the company is tackling power efficiency and scalability challenges at unprecedented levels.

You’ll join the Hardware Systems organization and take full ownership of rack-level power architecture
, defining and delivering the end-to-end power delivery strategy—from the power shelf through to the chip. This role is central to enabling performance, reliability, and efficiency across a massive AI compute platform.

What You’ll Do
  • Own the definition, design, and validation of the rack-level power architecture for a high-performance AI data center system
  • Collaborate closely with silicon, system, thermal, mechanical, and JDM partners to take power solutions from concept through production
  • Define power specifications, power management strategies, and accurate power estimation models across the full power delivery path
  • Design and integrate high-power voltage regulation solutions, including multi-phase VRMs and advanced power topologies
  • Lead lab validation and bring-up of complex power systems during initial silicon and system bring-up, executing workload testing to ensure clean, stable power delivery within tight tolerances
  • Drive compliance with industry standards and safety requirements, including electrical and thermal constraints
  • Provide technical leadership during rack integration, system debug, and cross-team design reviews
What We’re Looking For
  • 10–20 years of experience in power architecture and power system design for high-performance hardware
  • Deep expertise in rack-level power delivery
    , including power shelves and system-scale architectures (not board-level design)
  • Strong background with high-power topologies such as buck DC-DC converters, multi-phase VRMs, vertical power delivery
    , and GaN FET–based designs
  • Hands-on experience with transient modeling and simulation tools (Simplis, HSPICE) and schematic/layout tools such as Allegro
  • Proven lab bring-up, debug, and validation experience using standard power and measurement equipment
  • Track record of delivering shipped, production hardware
  • Familiarity with OCP Power Group standards and data center power architectures
  • Experience with 50V systems
    , with exposure to or direct experience designing 400V / 800V architectures strongly preferred
Why Join?
  • Join a well-funded, fast-growing company building next-generation AI data center infrastructure
  • Own one of the most critical subsystems in the platform:
    rack-scale power delivery
  • Work alongside senior engineers solving problems at massive scale
  • Hybrid role based in Mountain View, CA (3 days on-site, Tuesday–Thursday)
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