AMS SerDes Robustness Analysis Validation Architect

Summary

Are you inherently curious, hands‑on, and analytical? We are seeking a seasoned Ser Des Robustness Analysis & Validation Architect with a strong technical foundation and a hands‑on approach to drive the robustness, performance, and margin validation of high‑speed Ser Des PHYs, such as PCIe and USB, within our system. This role is ideal for someone who is motivated to push designs to the edge through intentional stress testing and margin‑finding techniques!

You will architect validation strategies that go beyond traditional spec‑checking, focusing on uncovering weaknesses in design assumptions, stress‑to‑fail conditions, and system interactions across wide‑ranging PVT and real‑world scenarios, including edge‑case behaviors. A deep understanding of Ser Des design and validation principles, SOC/system integration, and real‑world system environments is required. The role demands strong collaboration with design, architecture, and system teams to ensure the IP is designed with design for testability.

In addition, you will also partner closely with the validation team to help optimize for maximum test coverage versus execution time, ensuring efficient yet thorough validation. This is a hands‑on lab role that requires close collaboration with designers, architects, system, and test engineers to validate next‑generation Ser Des IPs from design conception through production.

• Define and architect margin‑to‑fail validation strategies to uncover weaknesses and failure conditions in high‑speed Ser Des PHYs across multiple process, voltage, temperature, and different system environments.
• Develop and implement stress‑to‑fail methodologies, covering end‑to‑end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc.
• Collaborate early with Ser Des design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design‑for‑test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc.
• Lead hands‑on lab experiments to validate assumptions, isolate issues, root‑cause failures, and fine‑tune test coverage for both standalone IP and system‑level interactions.
• Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints.
• Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates.
• Provide post‑silicon feedback that improves future architectural decisions, design margins, and validation methodology.
• Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for Ser Des validation.

• PhD in Electrical Engineering or related field with 10+ years of experience in Ser Des IP validation, AMS circuit design, or silicon/system‑level debug.
• Hands‑on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc., and measurement setups tailored for Ser Des PHYs.
• Deep understanding of high‑speed serial link protocols (PCIe, USB, Ethernet, Display Port, etc.) and equalization techniques (such as CTLE, DFE, FFE, etc.).
• Strong foundation in analog/mixed‑signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts.
• Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies.
• Proven ability to break down complex problems, isolate issues, and root‑cause at the circuit, protocol, and system levels.
• Demonstrated experience in design‑for‑validation, including fault injection, internal monitors, and behavioral hooks.
• Experience validating multi‑lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems.
• Familiarity with production and characterization flows, including margin‑to‑fail and stress testing techniques.
• Ability to guide test coverage optimization to reduce execution time without sacrificing…