Digital - SerDes Digital Design Lead

Join the leading chiplet startup! As the Ser Des Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will lead the digital design of Ser Des transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products.

You will work with a cross‑functional team of experts that operate from first principles, innovate and push the envelope to create high‑volume and high‑performance manufacturable products. We offer a fun work environment with excellent benefits.

• Lead the micro‑architecture definition and RTL implementation of high‑speed Ser Des digital blocks targeting 224G PAM4 and 448G signaling, including DSP‑based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
• Design and optimize PHY‑level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear‑boxing/rate‑matching logic
• Architect and implement forward error correction (FEC) encoder/decoder blocks including RS‑FEC (KP4/KP8), interleaving, and low‑latency FEC architectures optimized for 224G/448G link budgets
• Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
• Collaborate closely with analog/mixed‑signal designers on Ser Des AFE integration, digital‑to‑analog interface specification, calibration sequencing, and AMS co‑simulation bring‑up
• Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
• Define and implement auto‑negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
• Develop power‑efficient digital architectures with emphasis on clock gating, voltage scaling, and low‑power design techniques for data center and AI/ML interconnect applications
• Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next‑generation interconnect standards
• Design firmware‑accessible register interfaces, configuration/calibration logic, and DPI‑based firmware co‑simulation hooks for PHY bring‑up and debug
• Support post‑silicon characterization and debug activities; correlate silicon measurements with pre‑silicon simulation results to drive design improvements

• Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
• 12+ years of experience in digital design of high‑speed Ser Des, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
• Strong RTL design skills in System Verilog with deep understanding of synthesis, timing closure, CDC/RDC, and design‑for‑test (DFT) methodologies
• Expert‑level knowledge of Ser Des DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
• Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS‑FEC KP4/KP8), and/or die‑to‑die standards such as UCIe
• Hands‑on experience with high‑speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
• Experience working at the digital‑analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed‑signal simulation environments
• Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high‑growth environments
• Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus