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Senior Physical Design Engineer – AI SoC & 7nm

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: Eridu Corporation
Full Time position
Listed on 2025-12-15
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 210000 - 270000 USD Yearly USD 210000.00 270000.00 YEAR
Job Description & How to Apply Below
A Silicon Valley hardware startup is seeking an experienced physical design engineer to define SOC assembly and optimize performance in AI infrastructure. Candidates should have at least 10 years of experience, a relevant master's degree, and proficiency in Innovus or Synopsys tools. Skills in Verilog and scripting are necessary. Join a world-class team and impact the next generation of AI solutions.

The salary for this role ranges from $210k to $270k annually.
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Position Requirements
10+ Years work experience
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