Senior Technical Lead; Design | Verification

Our client is a world-leading technology company driving innovation in next-generation ASIC and SoC architectures. They are delivering cutting‑edge silicon for AI, high‑performance computing, and custom memory-intensive applications.

We are partnering on a strategic ASIC program involving advanced ARM-based architectures, chiplet/UCIe technologies, and custom high-speed memory interfaces. The program is already in motion, and a specialized 60/40 RTL Engineering – DV team is being built to accelerate critical design and verification milestones.

This role offers immediate technical impact: you will be contributing directly to the tape‑in of new custom IP, integrating complex third‑party components, and driving verification at scale.

• Lead design or verification of complex IP blocks, owning them end‑to‑end from specification through integration.
• Define specs, architecture, and microarchitecture for your blocks.
• Build, guide, or mentor teams on UVM verification environments and testbench architectures.
• Collaborate directly with senior client engineering leadership on critical technical decisions.
• Mentor junior engineers and ensure long‑term stability and continuity of the program.
• Support integration of third‑party IP into larger SoCs or subsystems.
• Optimize designs and verification strategies for performance, reliability, and scalability.

• 10+ years of experience in ASIC/SoC design or design verification (DV).
• Strong hands‑on experience with custom memory controllers/interfaces.
• Deep expertise in ARM-based ecosystems, including AMBA interconnects, buses, and debug infrastructure.
• Strong proficiency in RTL/Verilog/System Verilog, microarchitecture, synthesis, timing constraints, and lint/CDC checks.
• Demonstrated ability to own blocks independently, from specification to integration and verification.
• Proven experience in UVM-based verification, testbench architecture, and subsystem‑level verification.
• Comfortable representing engineering decisions to senior stakeholders.

• Experience with DRAM memory controllers.
• Experience with UCIe or other chiplet‑integration technologies.
• Prior leadership of complex IP block design/verification.
• Strong spec interpretation and documentation discipline.
• Demonstrated stability with long‑term program ownership.

This position is pivotal for the success of a strategic next‑generation ASIC initiative. You will have ownership of major IP blocks with immediate technical impact on AI and high‑performance computing roadmaps. This is a role for strong, independent technical leads who can operate confidently, mentor others, and scale with a rapidly evolving program.