Founding Senior RTL Design​/DV Engineer

This range is provided by Phinity. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

$/yr – $/yr

Today, every software engineer can 10x their productivity with tools like Cursor, but no DV engineer can do the same. Hardware lacks the training data that made automation of other domains possible. While software engineering leaped forward, chip design fell behind because 99% of hardware code is locked behind company walls. There is no path to automation unless someone breaks the data barrier.

Phinity is building the canonical training data infrastructure that will enable agentic hardware engineering.

We are building environments for agents to learn to design and verify chips. Our customers include one of the largest frontier model labs.

We're seeking hardware engineers to collaborate with frontier lab researchers to create high-quality RTL design, verification, and debugging challenges that mirror real-world semiconductor development. We are hiring a full-time industry veteran RTL engineer who can teach AI how to write good RTL and the most thorough test benches. This is the ground floor of hardware automation. The work you do here determines whether chip design enters the AI age or gets left behind.

Founding hires will receive generous equity compensation. This is an in-office role in our SF office.

• Lead the building of the hardest technical challenges in hardware design: design challenges across RTL generation, verification, debugging, timing closure, specification alignment. Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
• QA environments and manage overseas hardware teams
• Work directly with frontier lab AI researchers to understand agent capabilities and training requirements
• Shape the roadmap: you'll have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation and shape the data needed to achieve that future
• Bring your 5-10+ years of industry experience to decide what's automatable versus what still needs human judgment

• 5+ years in RTL design using Verilog/System Verilog or VHDL
• Experience with synthesis, timing analysis, and debugging tools
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)

• Strong problem-solving and analytical thinking
• Excellent communication skills for cross-functional collaboration for researchers who are not hardware experts
• Curiosity about AI/ML applications in hardware design
• Motivated by the mission of propelling a future of hardware automation

Mid-Senior level

Full-time

Information Technology

Technology, Information and Internet