ASICS Design Verification Engineer

Bachelor's degree in Engineering, Science, or a closely related field 2+ years of experience with ASIC design and verification tools, techniques, and methodology Master's degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field 6+ years of experience with ASIC design and verification tools, techniques, and methodology 6+ years of experience with digital design concepts and RTL languages such as System Verilog or Verilog, or VHDL.

6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills. 6+ years of experience with developing block-level testbench environment using System Verilog 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification 6+ years of experience with scripting/automation skills using either Perl or python

Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory) Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory) Bachelor's degree in Science, Engineering, or related field.