Speed Interface Micro Architect and RTL Design Engineer

Company: Qualcomm Technologies, Inc.

General

Summary:

The Mixed-Signal IP team at Qualcomm is seeking skilled digital design engineers to contribute to the development of next‑generation, high‑performance, low‑power interface IPs—including Ser Des, DDR, and die‑to‑die interconnects—for integration across Qualcomm’s product portfolio.

In this role, you will collaborate with a cross‑functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and requires a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

• Architect and define the digital design of high‑speed interface IPs (e.g., Ser Des, DDR, die‑to‑die) in close collaboration with system architecture and analog teams.
• Develop micro‑architecture and implement RTL for complex mixed‑signal IP blocks.
• Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA).
• Utilize industry‑standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design‑for‑test (DFT), synthesis, formal verification (FV), and static timing analysis (STA).
• Design and analyze DFT logic, including ATPG for stuck‑at fault (SAF) and transition delay fault (TDF) coverage.
• Create comprehensive design documentation, including hardware specifications.
• Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs.
• Work with the physical design (PD) team to support floor planning, placement, and timing closure of IPs.
• Support SoC integration and debug, including pre‑silicon simulation and post‑silicon bring‑up.

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands‑on experience in micro‑architecture and digital design for mixed‑signal IPs such as Ser Des, DDR, PLLs, DACs, ADCs, and sensors.
• Proficiency with industry‑standard ASIC design tools including Design Compiler, Prime Time, Power Compiler (PTPX), VCS, DFT Compiler, Spyglass, and others.

• Ph.D. in Electrical Engineering with 3+ years of industry experience in high‑speed digital circuit design.
• Strong background in low‑power digital design techniques.
• Expertise in computer architecture, digital signal processing, and algorithm development.
• Experience developing automation scripts and design productivity tools using Python or Perl.

• Bachelor’s degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• Ph.D. in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer.

Pay range: $ – $

If you would like more information about this role, please contact Qualcomm Careers.