CPU Design Senior Verification Engineer

Company

Qualcomm India Private Limited

Engineering Group, Engineering Group >
Hardware Engineering

Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.

• Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
• Work closely with design/verification teams within CPU to develop comprehensive test plan.
• Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
• Verify power intent through use of methodologies like UPF.
• Work closely with system architects, software teams and Soc team to validate system use cases.
• Work closely with emulation team to enable verification on emulators and FPGA platforms.
• Debug and triage failures in simulation, emulation and/or Silicon.

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• BE/BTech degree in CS/EE with 4+ years’ experience.
• Experience in power management verification.
• Implementation of assembly and C language embedded firmware.
• Experience in C/C++, scripting languages, Verilog/System Verilog.
• Strong understanding of power management features in CPUs and CPU based Socs.
• Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

• Good Understanding of CPU architectures and CPU micro-architectures.
• In-depth knowledge of digital logic design, micro-processor, debug features, and DFT architecture and microarchitecture.
• Experience with advanced verification techniques such as formal and assertions is a plus.
• Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE
  1500, MBIST, scan dump, memory dump is a plus.

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