Senior Staff Engineer

We are looking for a Design Verification Engineer to join our client’s high‑performance mixed‑signal IP verification team
. You will play a key role in verifying high‑speed interface and analog/mixed‑signal IPs that power next‑generation products in 5G, AI/ML, Compute, IoT, and Automotive markets.

You will be involved across the entire verification lifecycle
, from system‑level concept through tape‑out and post‑silicon validation, working closely with cross‑functional design and SoC teams.

• Define and develop pre‑silicon and post‑silicon test plans based on design specifications and industry standards.
• Architect and develop verification environments using System Verilog/UVM and advanced verification methodologies.
• Perform mixed‑signal verification
  , low‑power verification, formal verification, and gate‑level simulation.
• Develop assertions (SVA), testcases, coverage models
  , and ensure coverage closure.
• Debug complex design and verification issues across PHY, subsystem, and SoC levels.
• Collaborate with digital, analog, modeling, controller, and SoC integration teams to ensure successful verification and post‑silicon validation.
• Participate in post‑silicon bring‑up and validation activities
  .
• (Plus) Experience developing VIP from scratch for Ser Des controller + PHY is highly desirable.

• 2+ years of ASIC Design Verification or related experience.
• Strong knowledge of System Verilog/UVM and modern HVL verification methodologies.
• Experience with ASIC verification and formal tools such as:
• Experience with low‑power verification, formal verification, and gate‑level simulation
  .
• Solid understanding of standard protocols including:
• Hands‑on experience in mixed‑signal IP verification, including PLL, ADC/DAC, Ser Des, sensors, and high‑speed interfaces.
• Proficiency in scripting languages such as Python or Perl.