RTL Design Engineer

About Mirafra :

Mirafra is software service base organization started in 2004.

We are 500+ employees in India and 250+ In US.

Clear visibility to senior management which helps for constant professional growth.

• Design and verification experience including micro architecture, RTL design and test planning
• Timing closure experience including timing constraints and PTSI.
• Prior experience in digital and mixed signal circuit design for high speed PHYs
• Hands-on experience with System Verilog/Verilog, DFT insertion, and timing closure
• Hands-on experience with HVLs and Testbench architectures
• Exposure to high speed custom building blocks, such as, IOs, PLLs, DLLs, LDOs, etc.
• Excellent communication skills including documentation and the ability to work across multiple teams in multiple locations

• Design and verification experience including micro architecture, RTL design and test planning
• Timing closure experience including timing constraints and PTSI.
• Prior experience in digital and mixed signal circuit design for high speed PHYs
• Hands-on experience with System Verilog/Verilog, DFT insertion, and timing closure
• Hands-on experience with HVLs and Testbench architectures
• Exposure to high speed custom building blocks, such as, IOs, PLLs, DLLs, LDOs, etc.
• Excellent communication skills including documentation and the ability to work across multiple teams in multiple locations

• --Experience with LPDDR3/LPDDR4 protocols
• Experience in low power implementation techniques
• Experience in architecture, RTL design for high speed datapaths, linting, synthesis, STA, and DFT
• Experience in advanced digital CMOS processes nce in advanced digital CMOS processes

All your information will be kept confidential according to EEO guidelines.