Sr Lead IP Design Verification Engineer

Company:

Qualcomm India Private Limited

Engineering Group, Engineering Group >
Hardware Engineering/storage

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next‑generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimise, verify, and test حصہ electronic systems, bring‑up yield, circuits, mechanical systems, digital/analog/RF/optical, systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting‑edge, world class products.

Qualcomm Hardware Engineers collaborate with cross‑functional teams to develop solutions and meet performance requirements.

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Electrical Engineering or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Electrical Engineering or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Electrical Engineering or related field and 2+ years of Hardware Engineering or related work experience.

Join Qualcomm's design verification team in verifying the high‑speed mixed‑signal IP designs Tierra (PLL, DAC, ADC, Sensors, PCIe, USB, MIPI, CXL, C2C, D2D, DDR, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the design verification lifecycle, from system‑level concept to tape out and post‑silicon support.

• Define pre‑silicon and post‑silicon test plans based on design specs and using applicable standards, working closely with design team.
• Architect and develop the testbench using advanced verification methodology such as System Verilog/UVM, Functional Verification, UPF/Low power verification, Formal verification and Gate level simulation to ensure high design quality.
• Author assertions in SVA, develop test cases, coverage models, debug and ensure coverage closure.
• Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post‑silicon validation.

• Experience with Pre‑Silicon Verification, Low power design verification, Formal verification and Gate level simulation at IP/SS level.
• Experience in scripting languages (Python, or Perl).
• Experience with mixed‑signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Converters (DAC, ADC), or sensors will be

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