Sr. RTL Design Engineer - QGOV

Company

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

As a Design Engineer, you’ll play a critical role in shaping cutting‑edge digital designs.

• Design micro‑architecture for simple and complex digital interface blocks.
• Develop RTL code (Verilog/System Verilog) following industry best practices, handling multi‑clock, high‑frequency, low‑power, and low‑latency designs.
• Debug and troubleshoot issues during development and support post‑silicon bring‑up activities.
• Create comprehensive design documentation to ensure clarity and maintainability.
• Optimize designs for area, power, and performance metrics.
• Collaborate with DFT, implementation, verification, emulation, and firmware teams.

Must be based in San Diego full time, 5 days a week.

Applicants will undergo a government security investigation and must be eligible to receive a U.S. Government security clearance.

Must be a U.S. citizen.

• 5+ years of work experience with RTL/FPGA design (Verilog/System Verilog), embedded system architecture, and verification.
• Bachelor’s degree in computer science or electrical/electronics engineering (or related field) with 5+ years of hardware engineering experience, or Master’s degree with 5+ years of experience, or Ph.D. in a related field.

• Positive attitude and inclusive problem‑solving mindset.
• 5+ years of ASIC design experience.
• System Verilog expertise: linting, CDC, synthesis (FPGA and ASIC).
• Building test suites for design validation.
• Understanding of emulation and prototyping flows for design and validation.
• Experience designing complex digital logic blocks and subsystems (CPU, GPU, DSP, always‑on systems, digital interfaces such as PCIe, UART, I2C, DDRx, SPI, USB).
• Knowledge of ISAs such as ARM THUMB or RISC‑V.
• Understanding of processor or microcontroller system design.
• Experience with multi‑power domain and multi‑clock domain designs.
• Proficiency in scripting or automation languages like Python or Perl.
• Familiarity with industry‑standard digital design tools.
• Awareness of challenges with lower‑node technologies.

• Bachelor’s degree in science, engineering, or related field and at least 2 years of ASIC design, verification, validation, integration, or related experience.
• Master’s degree in science, engineering, or related field and at least 1 year of ASIC design, verification, validation, integration, or related experience.
• Ph.D. in science, engineering, or related field.

Pay range: $ - $. Qualified employees may also receive a discretionary bonus program and RSU grants.

Qualcomm is an equal‑opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.

Qualcomm is committed to providing an accessible hiring process. If you are an individual with a disability and need accommodations, email disabilit

For more information about this role, contact Qualcomm Careers.