Senior Formal Verification Engineer

Company:
Job Area: General

Summary:

QCT's Digital ASIC design team delivers cutting edge hardware and software products that power the user experience and graphics content of the most advanced mobile devices on the market.

Graphics formal verification positions involve the development of high‑quality formal verification test benches to verify complex designs in GPU. The position involves working with design and implementation teams to verify designs with high quality. Candidates must be proficient in debugging, deep bug hunting, formal tools, formal verification methodologies and processes. They should also be proficient in design debug and assertion development.

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of software engineering, hardware engineering, systems engineering, or related work experience.
• Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of software engineering, hardware engineering, systems engineering, or related work experience.
• PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of software engineering, hardware engineering, systems engineering, or related work experience.

Job Description:

• Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platforms.
• Develop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance.
• Drive debug failures on emulator using latest technologies. Work with designers and SW driver team for test plan and debug.
• Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL.
• Work on third‑party IP integration and system‑level debugging.
• System level RTL simulation & design verification.
• Support chip bring‑up and post‑silicon debug.
• Debug functional and timing models.

Preferred Qualifications:

• Bachelors degree in Science, Engineering, or closely related field.
• 1+ years of hands‑on experience in emulation/simulation acceleration/FPGA.
• 1+ years in design validation/Post‑silicon debug.
• 1+ years of hands‑on experience creating high‑performance & area‑efficient emulation environments from RTL.
• 1+ years of hands‑on experience in emulator platforms, platform bring‑up, digital design, verification, debugging, and waveform viewers.
• 1+ Hardware emulators, such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs.
• 1+ Emulation methodologies, including in‑circuit emulation, hybrid systems, or simulation acceleration.

Desirable

Skills:

• MS degree in Electrical Engineering or equivalent; 1 year of practical experience.
• Design Verification knowledge – UVM/System Verilog preferred.
• Knowledge of GPU/CPU/DDR/Bus preferred.
• Verilog and System Verilog experience.
• Debugging system‑level software, Debug RTL.
• Programming skills in C and C++.
• Scripting in Python, Tcl, or Perl.
• Knowledge of Vendor Emulation tools/Xilinx tools/Synthesis tools.

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EEO

Employer:

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary…