Custom IP Design Engineer

Company

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

General

Summary:

Qualcomm is one of the fastest growing semiconductor organizations, making high-end chips with the most advanced technologies. To support its growing needs, we have a Custom Solutions Team for design and development (RTL to GDS) of various highspeed and low power IPs (mini-macros) which are used across different sub-systems in SoC. In this position, you will be an integral part of the team with the opportunity to experience the entire ASIC design flow.

This position involves the design and development of best-in-class custom digital IP from RTL to GDS for optimizing SoC Power, Performance and Area (PPA). It includes the IP specification definition, RTL design, architecture and circuit design, physical implementation, verification and sign offs. Candidates with coding and flow support experience are preferred.

Job Responsibilities:

• Use industry standard and internally developed tools and flows (Cadence, Innovus, HSPICE, Primetime etc) to execute architecture or circuit level design with defined specifications.
• Oversee the IP implementation through various design stages: RTL development, Transistor level analysis, Place and Route implementation and Timing closure
• Simulate and sign off design margin and PPA metrics.
• Generate and release IP collaterals (functional/DFT/timing models, LEF abstract, DEF, etc) for SoC consumption.
• Conduct design reviews and documentation.
• Flow and methodology enablement support.
• Close collaboration with different teams across various time zones.

Skillset/

Experience:

• Strong background and exposure in one of the digital design areas:
  • Experience of digital library architecture and circuit design, and simulation sign off (HSPICE), such as custom circuit, standard cell or SRAM.
  • Experience with transistor level circuit analysis flows: ESPCV, Spice, Monte Carlo simulations, Nanotime
  • Experience with synthesis, physical design flows (Genus, Innovus or Fusion Compiler) and STA timing closure (Prime Time or Tempus).
• Knowledge of semiconductor device physics and behavior; understanding advanced technology, such as FinFET, Gate All Around is a plus.
• Adaptive to non-standard design flow.
• Programming skill in python, perl, tcl, shell is a strong plus.
• Variation-aware design experience is a plus.
• Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field.

EEO

Employer:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email disabilit Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Qualcomm expects its employees to abide by all applicable policies and procedures, including security requirements regarding protection of confidential information, to the extent permissible by law.

Pay range and Other Compensation & Benefits: $ - $

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is one component of total compensation, and Qualcomm also offers a competitive annual discretionary bonus program and opportunity for annual RSU grants. Our benefits package is designed to support your success at work, at home, and r recruiter can discuss details about Qualcomm benefits.

If you would like more information about this role, please contact Qualcomm Careers.