ASIC Design Verification Engineer; Security Group

Company: Qualcomm Technologies, Inc.
Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products.

Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements.

As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product.

• Work with subsystem and SOC Architects to understand the concepts and high-level system requirements.
• Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture.
• Develop Verification Methodology, ensuring scalability and portability across environments.
• Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Cover points.
• Develop Verification Plans and Test benches for your functional domain.
• Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures.
• Track and report DV progress using a variety of metrics, including Bugs and Coverage.

• Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating.
• Solid understanding of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes.
• Advanced techniques such as:
  Formal, Assertions, and Silicon bring-up, is helpful.
• In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures.
• Experience in writing Testplans, portable Test benches, Transactors, and Assembly code.
• Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification.
• Ability to develop and work independently on a Block/Unit of the design.

Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understanding of UNIX commands and Python/Perl scripting

• Bachelor s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here…