Senior​/Firmware Engineer — Hardware Architecture

About 1X

We’re an AI and robotics company based in Palo Alto, California, on a mission to build a truly abundant society through general‑purpose robots capable of performing any kind of work autonomously.

We believe that to truly understand the world and grow in intelligence, humanoid robots must live and learn alongside us. That’s why we’re focused on developing friendly home robots designed to integrate seamlessly into everyday life.

We’re looking for curious, driven, and passionate people who want to help shape the future of robotics and AI. If this mission excites you, we’d be thrilled to hear from you and explore how you might contribute to our journey.

We are looking for a cross‑functional Firmware / Embedded Engineer to develop and maintain low‑level firmware that supports and enables system‑level hardware architecture. In this role, you will focus on robust, maintainable, and well‑structured embedded software that spans multiple hardware domains and directly informs architectural decisions.

You will work closely with hardware architects, electrical engineers, systems engineers, and test engineers to ensure firmware reliably bridges hardware capabilities and higher‑level system requirements across prototype and production platforms.

The system is a humanoid robot with 20+ distributed embedded nodes that must communicate deterministically, fail safely, and operate continuously in uncontrolled environments. This is a new product category. Established playbooks from adjacent industries are useful starting points, but many of the problems you will encounter do not have known solutions. The ideal candidate reasons from first principles, works comfortably at the boundary between firmware and hardware, and is energized rather than frustrated by problems that require novel approaches.

• Develop and maintain firmware for the deterministic communication bus connecting 20+ embedded nodes to a central controller, including cyclic data exchange, distributed clock synchronization, and protocol state management
• Design real‑time data interfaces and acyclic communication channels for device configuration, parameterization, and runtime diagnostics
• Architect safety communication firmware that delivers safe shutdown commands within deterministic time bounds, using black channel principles (independent CRC, watchdog, sequence validation) over untrusted transport
• Responsible for the testing, validation, and verification of initial firmware releases to ensure functionality, reliability, and performance requirements are met
• Integrate network‑based safety functions with hardware mechanisms including external watchdogs, gate driver enables, and hardwired safe‑state paths
• Collaborate with hardware architects to define interfaces, requirements, and trade‑offs; support bring‑up, integration, and debugging of new platforms
• Implement drivers and hardware abstraction layers for embedded bus interface (CAN, CANopen, SPI, I²C, UART) used for communication with battery management, sensors, and peripheral ICs.
• Design secure boot loader architecture with cryptographic signing and validated rollback for firmware updates delivered over the communication bus
• Develop diagnostic and telemetry infrastructure: logging, error counters, communication statistics, and DFT hooks for production end‑of‑line validation
• Evaluate network topology and redundancy strategies for production, considering failure domain isolation and physical routing constraints within a mobile form factor
• Document firmware architecture, interfaces, and assumptions; improve code structure, readability, and maintainability

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field

• 7+ years of industry experience with embedded systems and real‑time firmware development
• Proficiency in C and C++ for embedded targets
• Deterministic communication experience — production‑level work implementing, debugging, or substantially modifying a real‑time communication stack on embedded hardware. The candidate should understand at a fundamental level how cyclic data exchange, clock synchronization, and protocol state machines work,…