ASIC Intern

ASIC Intern

Who We Are:

Hewlett Packard Enterprise is the global edge‑to‑cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.

Our culture thrives on finding new and better ways to accelerate what’s next. We value varied backgrounds and provide flexibility to manage work and personal needs. We make bold moves together and are a force for good.

Job Description:

Aruba, a Hewlett Packard Enterprise Company, is a leading provider of next‑generation networking solutions for the mobile enterprise. We have an exciting opportunity for an ASIC Post‑Si Verification Engineering Intern to join our team in Roseville, CA.

The company designs and delivers Mobility‑Defined Networks that empower IT departments and the new generation of tech‑savvy users who rely on their mobile devices for every aspect of work and personal communication. To create a mobility experience that the new generation and IT can rely upon, Aruba Mobility‑Defined Networks automate infrastructure‑wide performance optimization and trigger security actions that used to require manual IT intervention.

The results are dramatically improved productivity and lower operational costs.

• The intern will work with the HPE Aruba ASIC development team on next‑generation products. The summer project will be used in the development activities of current or future ASICs, contributing at a high level.
• Work with and learn from senior members of the ASIC/VLSI team. Responsibilities may include RTL/Physical Design, Pre‑Silicon verification, Post‑Silicon verification, Formal Verification, script and/or tool development, schedule breakdowns, document generation, and other duties based on student skills and business needs.

• Currently pursuing a Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering or a related technical field.
• At least the 3rd year of engineering courses completed.

• Basic programming or scripting knowledge (e.g., Verilog, System Verilog, Python, PERL, TCL, C, C++).
• Experience with hardware design.
• Strong interest in high‑tech and a passion for learning.
• Excellent communication and interpersonal skills.
• Strong problem‑solving and analytical skills.
• Ability to work within a team environment.

• University students actively enrolled in a Bachelor's program, typically working during school breaks and returning to their university. Opportunities for full‑time students to work part‑time during the school year may exist in some countries.

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports physical, financial and emotional wellbeing.

Personal & Professional Development

We invest in your career, offering programs to help you reach any career goals you have—whether you want to become a knowledge expert or apply your skills elsewhere.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We value diverse backgrounds and provide flexibility to manage work and personal needs.

We provide competitive hourly compensation for this internship.

Hourly Salary USD 35.00 – 40.25 in California. The listed salary range reflects base salary; variable incentives may also be offered.

Information about employee benefits offered in the US can be found at

HPE is an Equal Employment Opportunity Employer. We do not discriminate on the basis of race, gender, or any other protected category. All decisions are based on qualifications, merit, and business need. We are committed to inclusion of veterans, individuals with disabilities, and the LGBT community.

HPE and its authorized recruitment agencies will never charge any candidate a registration fee or hiring fee. Candidates should verify the legitimacy of any agency. HPE disclaims liability for any damages or claims resulting from fraudulent representations.