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Senior RTL Design Engineer Networking ASIC
Job in
Roseville, Placer County, California, 95678, USA
Listed on 2026-03-06
Listing for:
Hewlett Packard Enterprise Company in
Full Time
position Listed on 2026-03-06
Job specializations:
-
Engineering
Systems Engineer
Job Description & How to Apply Below
A leading global technology firm is seeking a Senior RTL Design Engineer to join their HPE Networking ASIC organization. This role involves architecting complex modules for high-performance networking chips, writing specifications, and collaborating with cross-functional teams. Candidates should have a Bachelor's degree in Electrical Engineering and at least 10 years of experience, with strong Verilog/System Verilog skills and knowledge of EDA tools.
Competitive salary range from $153,500 to $310,500, depending on experience and location.
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Position Requirements
10+ Years
work experience
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