Senior RTL Design Engineer -Speed ASICs
Job in
Roseville, Placer County, California, 95678, USA
Listed on 2026-03-05
Listing for:
Hewlett Packard Enterprise
Full Time
position Listed on 2026-03-05
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A global technology company is seeking a Senior RTL Design Engineer to join its fast-paced chip design group in California. The ideal candidate will have extensive experience in VLSI design, particularly for high-speed ASICs, and a strong background in Verilog or System Verilog. Responsibilities include architecting complex modules and collaborating with cross-functional teams to ensure successful implementation.
This role offers the opportunity for personal growth in a collaborative environment and is designed for onsite work.
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Position Requirements
10+ Years
work experience
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