Senior Digital Verification Engineer

As the global leader in high‑speed connectivity, Ciena is committed to a people‑first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well‑being, and belonging. We are a technology company that leads with our humanity, driving our business priorities alongside meaningful social, community, and societal impact.

We are looking for an enthusiastic digital verification engineer to be involved in the verification of the Wavelogic family of products, working within a team of digital design engineers, verification engineers, and architects. Your role will be to propose and implement innovative verification strategies, thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family based out of our Pittsford, New York office.

• Read and understand the architecture and functional requirements specification documents and collaborate with systems engineers and architects.
• Validate one or more architectural functional blocks using simulation, formal and coverage methods.
• Create verification, functional coverage and formal verification test plans.
• Develop testbench environments and components (agents, scoreboard, scenarios) using System Verilog UVM and/or C where applicable.
• Perform coverage‑driven verification, monitor regressions and debug failures with the function designer.
• Report status updates on a regular basis.

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level.
• Highly motivated self‑starter, able to work independently and as a team player.
• Ability to solve complex technical problems methodically.
• Excellent organization and written & oral English communication skills.
• Proficiency above the intermediate level with System Verilog, SVA, and major vendor simulators.
• Proven ability to determine appropriate and comprehensive digital verification and coverage strategies.

• Experience with UVM.
• Experience with formal verification methods.
• Experience in DSP and/or Forward Error Correction.
• Experience with mixed‑signal design validation.
• Experience with standards and protocols such as OTN, B100G, Ethernet.
• Experience with Jira for bug tracking and GIT for source code management.
• Familiarity with programming languages such as Python, Make, Bash, object‑oriented programming, C, C++, System C.

The annual pay range for this position is $119,900 – $191,500.

Ciena offers a comprehensive benefits package that includes medical, dental, vision, 401(K) and DCPP matching, Employee Stock Purchase Program, Employee Assistance Program, paid holidays, sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building an environment where employees feel respected, valued, and heard. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If you have an accommodation need, please let us know.