Senior FPGA Engineer, LEO Payload FPGA, Leo Hardware Development

Description

LEO is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity.

Create FPGA solutions to support LEO’s satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. The FPGA design engineer will work with systems teams to define, develop, implement, test, and release FPGA-based solutions to enable LEO. This will focus on creating digital designs for networking functions using the latest generations of FPGA technologies and modern FPGA design processes and tools.

• Have ownership of one or more FPGA bitstreams.
• Create and release FPGAs through the development phases of uArchitecture, RTL Design, Physical Implementation, Timing Closure, Simulation Validation, and Lab Based Silicon Validation.
• Collaborate with network communication system architects to define and design, implement, test, release, and support networking functions targeted to FPGA technology.
• Collaborate with Digital Communications/Networking system architects and design engineers to implement digital logic functions in FPGAs.
• Collaborate with system architects and design engineers to implement digital logic functions in FPGA prototypes to validate and trade‑off architecture & design alternatives.
• Collaborate with systems architects, HW engineering design teams & FW/SW design teams to bring up and test systems combining FPGA, firmware, RF, and Networking functions.
• Drive trade‑off analysis to benefit customer experience and optimization of target technology resources for cost, size, power, performance, and features.
• Export Control Requirement:
  Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA design efforts for Versal ACAP and IGLOO2 platforms from concept through production.
• Develop and optimize RTL code for high‑performance, resource‑efficient designs.
• Perform timing analysis, synthesis, place and route, and design verification.
• Create comprehensive test benches and simulation environments.
• Collaborate with cross‑functional teams including hardware engineers, software developers, and system architects.
• Debug and troubleshoot FPGA designs at both simulation and hardware levels.
• Develop technical documentation including design specifications, test plans, and user guides.
• Support hardware integration, manufacturing, and production deployment activities.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 7+ years of FPGA design experience.
• Experience with AMD Xilinx Versal ACAP FPGA architecture and development tools.
• Demonstrated expertise with Microchip IGLOO2 FPGA platform.
• Strong proficiency in Verilog HDL for RTL design and verification.
• Experience with FPGA design tools (Vivado, Libero SoC, or equivalent).
• Solid understanding of digital design principles, timing analysis, and clock domain crossing.
• Experience with simulation tools (Model Sim, VCS, or similar).
• Strong debugging and problem‑solving skills.
• HDL
  
  Languages:
  
  Verilog (required), System Verilog (preferred).
• FPGA Platforms:
  Versal ACAP, IGLOO
  2.
• Design Tools:
  Xilinx Vivado, Microchip Libero SoC.
• Simulation:
  Model Sim, Vivado Simulator, or equivalent.
• Scripting:
  Python, TCL, or Perl for design automation.
• Protocols:
  Understanding of industry‑standard communication protocols.

• Experience with System Verilog and UVM methodologies.
• Knowledge of high‑speed interfaces (PCIe, DDR, Ethernet, Ser Des).
• Familiarity with embedded systems and hardware‑software integration.
• Experience with…