Data & IO Design Engineer

Company Description

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas.

Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions.

You can be part of the takeoff of an innovative business that develops cutting‑edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization.

We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team‑oriented, inclusive, results driven, collaborative, passionate, and flexible.

Key Responsibilities:

• Design and develop high-speed IO and data interface circuits, including drivers, receivers, clocking, and serialization/deserialization (Ser Des) components.
• Work closely with system architects and RTL designers to define interface requirements, signal integrity constraints, and performance targets.
• Perform circuit- and system-level simulations (e.g., SPICE, IBIS-AMI, HSPICE) to validate signal integrity and timing under process, voltage, and temperature (PVT) variations.
• Collaborate with package and board design teams to co‑optimize high-speed signaling paths for performance, reliability, and manufacturability.
• Support bring‑up, debug, and validation of IO interfaces in silicon and system‑level test environments.
• Contribute to post-silicon characterization, tuning, and root cause analysis of signal integrity and margin issues.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 10+ years of experience in high-speed digital or mixed-signal IO design.
• Strong understanding of high-speed signaling fundamentals including impedance matching, crosstalk, jitter, and equalization.
• Hands‑on experience with EDA tools for layout-aware simulation, signal integrity (SI), and timing analysis.
• Familiarity with interface standards such as PCIe, ONFI, LPDDR, or similar high-speed memory protocols.

Preferred Qualifications:

• Experience designing IO for NAND Flash, SSD controllers, or other high-bandwidth memory/storage applications.
• Knowledge of packaging effects, board-level parasitic, and system co-design practices.
• Proficiency in scripting (Python, Perl, or Tcl) for simulation automation and analysis.
• Excellent problem-solving skills and ability to work across cross-functional hardware and validation teams.

The compensation range for this role is $139,520‑$223,300. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.