AI Frameworks Architect

The Intel NPU IP Architecture team is looking for an AI Frameworks Architect to lead VPU architecture performance modeling and analysis activities.

In this position, you will function as a senior technical member in the NPU architecture performance COE team. The primary responsibility of the team includes developing the next generation NPU architecture performance model and conducting performance analysis using models from various benchmarking suites or customer end-to-end use cases.

• Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
• Implementing and testing performance models with systematic SW development practice.
• Conduct performance-and-power analysis of various neural network workloads.
• Utilize the performance data-driven flow to drive the NPU architecture definition.
• Collaborate with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
• Perform pathfinding, survey technologies, participate in standards committees, and present at external and internal events.
• Interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science (or related) with 6+ years of relevant experience OR Master's Degree with 4+ years OR PhD with 2+ years.
• 6+ years of experience in two or more of the following:
  • Knowledge of computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW, multi-core/multi-threading, data precision, memory hierarchy.
  • Understanding hardware modeling concepts such as event-driven, concurrency, etc.
  • Knowledge of AI frameworks, AI models and basic neural computing operations.
  • Knowledge of data precision, floating point vs fixed point computing trade-offs.

• Experience with object-oriented programming in C/C++ or Python; capable of designing class objects, data structures, and API methods.
• Prior usage of event-driven modeling language (SC/C++/Python) and platforms.
• Prior experience in architecture definition and/or mentoring junior engineers.

Experienced Hire

Shift 1 (United States of America)

Primary: US, California, Santa Clara. Additional locations: US, Arizona, Phoenix; US, California, Folsom; US, Oregon, Hillsboro; US, Oregon, Portland.

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, or any other characteristic protected by local law.

Annual Salary Range for US locations: $168,100 - $299,040 USD. The final salary depends on location and experience.

This role will require an on-site presence.

Mid-Senior level

Full-time

Design, Art/Creative, and Information Technology