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Design Verification Engineer: ASIC​/VLSI; SystemVerilog​/UVM

Job in Phoenix, Maricopa County, Arizona, 85003, USA
Listing for: Emonics LLC
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Design Verification Engineer: ASIC/VLSI (SystemVerilog/UVM)
A technology firm seeks a Design Verification Engineer to ensure the functional correctness and reliability of complex semiconductor designs. This role involves developing verification environments and validating designs prior to tape-out. Ideal candidates will have a Bachelor’s or Master’s degree in Electrical Engineering or related field, strong digital design knowledge, and expertise with UVM and simulation tools. Responsibilities include execution of verification plans, RTL debugging, and continuous improvement of methodologies.
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