Senior Director, IO Analog Design Engineering

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** Welcome!**## .Senior Director, IO Analog Design Engineering page is loaded## Senior Director, IO Analog Design Engineering locations:
US, Arizona, Phoenix:
US, Colorado, Fort Collins:
US, California, Santa Claratime type:
Full time posted on:
Posted Todaytime left to apply:
End Date:
March 18, 2026 (27 days left to apply) job requisition :
JR0281112#
** Job Details:**##

Job Description:

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As the senior engineering leader for this global organization, you will shape Intel's future of IO and chiplet interconnect technology.

This leader will be responsible for the following:
* Setting and continuously refining a multi-generational roadmap for HSIO and D2D IP development, anticipating market and technology trends and architectural shifts and driving alignment across SoC, platform and product teams.
* Engaging directly with senior Intel architects and executives to define IP landing zones and build execution plans
* Driving IP development across architecture, logic, validation and analog design teams, while collaborating tightly with test chip, structural design and layout teams.
* Managing competing requirements, schedules, and resource balancing across multiple functional teams, including multi-site resource planning.
* Ensuring high quality and on-time IP delivery, including proactive risk management throughout the development lifecycle.
* Leading, growing and developing a high-performing global team of engineers across US and India, driving organizational clarity and alignment.
* Fostering a culture where issues surface and are addressed early.
* Driving efficiency throughout the development cycle, including the adoption of AI solutions across all job functions. Intel is building products that power the world and every silicon design has analog IP. This is an opportunity to shape the silicon products of the future and lead an incredible team of engineers.##
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* Qualifications:

** Minimum Qualifications
* Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 12+ years of experience
* Proven deep experience in analog IP development and delivering from concept to launch.
* 10+ years of proven success building, leading, and driving execution in silicon teams delivering to complex, high-impact programs

Preferred Qualifications
* 10+ years of experience leading analog IP design teams.
* Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe.
* Demonstrated success managing global, multi-disciplinary engineering organizations.
* Experience navigating complex SOC customer negotiations.## Job Type:Experienced Hire##

Shift: Shift 1 (United States of America)## Primary

Location:

US, Arizona, Phoenix## Additional Locations:

US, California, Santa Clara, US, Colorado, Fort Collins## Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.## Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of Trust This role is a Position of Trust.

Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.## Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $- USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by…