Collateral Device Engineer

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** Welcome!**## .Collateral Device Engineer page is loaded## Collateral Device Engineer locations:
US, California, Santa Clara:
US, Arizona, Phoenix:
US, Oregon, Hillsborotime type:
Full time posted on:
Posted Yesterday time left to apply:
End Date:
February 12, 2026 (26 days left to apply) job requisition :
JR0279569#
** Job Details:**##

Job Description:

** About MDCE
** Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development.
** Position Overview
** As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications.
** Key Responsibilities*
* • Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring
• Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements
• Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications
• Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing
• Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities
• Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms
• Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability
• Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers
• Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies.
** Ideal candidate must demonstrate:*
* • Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs
• Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions
• Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment
• Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization##
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* Qualifications:

**** Minimum Qualifications*
* • Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development.

The years of experience must include:
• Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
• Experience in scribe line layout design and process monitoring structure development.
• Proficiency in design rule development, validation, and waiver management processes.
• Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design.
** Preferred Qualifications*
* • Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development
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