Senior Silicon Application Engineer; Packaging Design

Position: Senior Silicon Application Engineer (Packaging Design)
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** Welcome!**## .Senior Silicon Application Engineer (Packaging Design) page is loaded## Senior Silicon Application Engineer (Packaging Design) locations:
US, Arizona, Phoenix:
US, California, Santa Clara:
US, Oregon, Hillsborotime type:
Full time posted on:
Posted Todayjob requisition :
JR0279351#
** Job Details:**##

Job Description:

** About Intel Foundry Services
** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
** Position Overview
** We seek a highly motivated, results-driven Senior Silicon Applications Engineer (Packaging Design) to join our team within Intel Foundry Aerospace, Defense and Government (ADG). This role focuses on advanced packaging technologies, working closely with foundry customers to define, develop, and implement design tools, flows, and methodologies for system co-design, implementation, and verification. You will serve as the technical expert on packaging design tools while consulting on design and implementation challenges.
** Key Responsibilities
**** Customer Technical Leadership
*** Establish technical credibility, building trust and strong relationships with Intel Foundry ADG customers
* Ensure customers successfully evaluate, adopt, and design products using Intel process technology
* Serve as primary technical expert on packaging design tools and implementation methodologies
* Provide clear communications and technical guidance to customers and stakeholders
* Analyze customer design issues and environments to define functional specifications for EDA vendors
* Drive adoption of advanced packaging verification methodologies including signal integrity and power integrity
** Advanced Packaging Solutions
*** Work closely with customers on advanced packaging technologies including multi-die/3

DIC platforms
* Support design implementation and verification across complex packaging architectures
* Consult on packaging design challenges and provide innovative technical solutions
** Cross-Functional Collaboration
*** Synthesize complex technical information and lead in-depth tactical discussions with customers
* Collaborate with Intel engineering teams to address customer requirements and technical challenges
* Support customer evaluations and design reviews for advanced packaging implementations
* Drive results through highly organized, analytical approach and strong teamwork
** Core Competencies
*** Strong technical credibility and customer relationship building skills
* Highly organized, analytical mindset with strong team collaboration abilities
* Excellent communication skills for complex technical discussions
* Results-driven approach with ability to deliver customer success outcomes##
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* Qualifications:

** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
** Minimum Qualifications
*** US Citizenship required
* Ability to obtain US Government Security Clearance
* Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
* 7+ years of experience in Package Design and relevant EDA tools
* Experience interfacing with customers and/or stakeholders
* Experience analyzing customer design issues, environments, and defining functional specifications for EDA vendors
** Preferred Qualifications
*** Active US Government Security Clearance with a minimum of Secret Level.
* Post-graduate degree in Electrical/Computer Engineering or STEM-related field
* Experience with Advanced EDA Tool
* Experience with Multi-die/3

DIC Platform Tools:
Cadence Integrity, Synopsys 3

DIC…