Technical Coordinator – Horizon EU Project

Technical Coordinator – Horizon EU Project

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About Us

Axelera AI is not your regular deep-tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just four years, we have raised a total of $120 million and have built a world‑class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Are you up for the challenge?

We are seeking a Technical Coordinator to represent Axelera AI in a major Horizon EU program developing next‑generation RISC‑V AI chiplets for high‑performance computing. The ideal candidate has strong HPC hardware, AI acceleration, and ASIC design expertise, paired with excellent project coordination and stakeholder‑management skills. You will translate project requirements into clear technical strategies, manage consortium interactions, and ensure alignment with EU objectives while allowing our internal teams to stay focused on execution.

As Axelera AI’s key liaison to the consortium, you will oversee coordination, reporting, and strategic planning, ensuring our technical contributions meet project goals and align with our internal roadmap.

• EU Project Strategy Lead:
  Drive Axelera AI's technical strategy for the EU project and translate consortium requirements into clear actionable guidance across architecture, silicon, software, machine learning, and system integration teams.
• Consortium Technical Interface:
  Serve as the primary technical contact for the project partners, manage all partner communication, coordinate regular meetings and day‑to‑day project interactions, and participate in in‑person project events including all‑hands meetings, technical workshops, and consortium gatherings.
• Technical Cross‑Domain Problem Solver:
  Facilitate resolution of technical challenges in accelerator architecture, SIP & PCB design, machine integration, and AI workload optimization, making autonomous decisions on consortium matters and escalating critical issues when necessary.
• Internal Alignment Manager:
  Collaborate closely with program management to support project‑related road‑mapping, lead annual Project Plan updates, monitor Work Package progress, and coordinate and enable timely delivery of all project deliverables while tracking critical paths, dependencies, and risks; translate consortium requirements into actionable plans that align with internal priorities and minimize workflow conflicts.
• EU Reporting & Compliance Lead:
  Lead preparation of technical reports for EU submissions, represent Axelera AI at coordination meetings, and ensure Horizon EU compliance; coordinate with finance team on effort reporting and cost tracking, validate submissions, and support audit preparation while minimizing administrative burden on technical staff.

• Proven experience as Technical Lead or Coordinator in Horizon EU or similar multi‑partner collaborative research projects, including demonstrated knowledge of EU reporting requirements, deliverable management, and consortium coordination. Strong organizational and problem‑solving abilities with proven capacity to manage multiple work streams, anticipate issues, and work autonomously in complex multi‑stakeholder environments.
• Advanced degree (Masters & above) in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years experience in HPC hardware and AI acceleration projects.
• Strong technical background across computer architecture, ASIC design, AI/HPC systems, and AI software stack, including hands‑on experience with multi‑node architectures, virtual prototyping, ASIC design, SIP…