Hardware Engineer

Base Pay Range

$/yr - $/yr

Acceler8 Talent is partnered with a seed‑stage startup ushering in a new generation of AI‑driven chip development. This team is building the intelligence layer that compresses the path to tape‑out from years to months and is hiring a Founding Hardware Engineer to help shape this next era of silicon.

Their technology amplifies hardware engineering teams across DI, DV, and PD workflows, assists in building IP from scratch, and keeps human experts fully in control throughout the process. Originating from academic research and growing quickly, the company brings together cutting‑edge ML and deep semiconductor expertise to redefine a trillion‑dollar industry.

• Drive RTL design and verification efforts that power the platform’s AI‑assisted chip design capabilities.
• Own hardware evaluation frameworks and lead benchmarking and analysis initiatives.
• Partner with ML engineers to convert hardware needs into precise, actionable specifications.
• Build and scale hardware testing infrastructure used to validate AI‑generated designs.
• Engage directly with clients to gather hardware requirements and communicate them to internal technical teams.
• Architect end‑to‑end hardware evaluation pipelines, from requirements capture through full validation.

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline.
• Prior work on a chip‑design or tape‑out team (e.g., NVIDIA, Synopsys, Cadence). For founding‑level roles, at least 5 years of industry experience.
• Strong Python and Bash skills; capable of writing scripts, pipelines, and CI/CD tooling around EDA workflows.
• Hands‑on experience with common Synopsys/Cadence tools (Xcelium, Genus, Innovus, etc.) and associated TCL‑based flows.
• Specialization (one of the following):
• Design Integration / RTL / Architecture:
  Experience creating complex IP in System Verilog.
• Design Verification:
  Proficiency in UVM and System Verilog‑based verification methodologies.
• Physical Design:
  Background in synthesis, floor planning, P&R, timing closure, or physical verification on advanced‑node designs.

• Experience on AI‑for‑chip‑design initiatives (e.g., at Synopsys, Cadence, NVIDIA) or familiarity with DFT or power‑optimization flows.
• Methodology/flow development experience, especially building production systems that coordinate handoff across multiple design stages.