ASIC Verification Engineering Intern
Job in
Ottawa, Ontario, Canada
Listed on 2026-01-13
Listing for:
Advanced Micro Devices, Inc
Full Time, Apprenticeship/Internship
position Listed on 2026-01-13
Job specializations:
-
IT/Tech
Systems Engineer, Electrical Engineering -
Engineering
Systems Engineer, Electronics Engineer, Software Engineer, Electrical Engineering
Job Description & How to Apply Below
We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you!
We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career!
JOB DETAILS :
Location:
Ottawa, ON, Canada Onsite/Hybrid:
This role requires the student to work full time in a hybrid or onsite work structure throughout the duration of the co-op/intern term. Duration: 12 or 16 months. Starting May 4, 2026 WHAT YOU WILL BE DOING:
You will join our team of experts developing ASIC and Adaptive SoC intellectual property (IP) for the next generation communication networks and data centers. You’ll work with a highly motivated team of engineers developing advanced verification environments for best-in-class configurable silicon targeted for wired communication applications such as AMD’s MI Series Accelerators and Versal SOCs Contribute to the development of advanced Systemverilog-UVM based verification environments and IP components Write tests, sequences, and testbench components in System Verilog and UVM to achieve verification of the design Learn to employ a Coverage-Driven Verification methodology with Constrained Random Stimulus Review and contribute to verification plans and design specifications Contribute to process improvements via automation of tasks and exploring and evaluating new tools and methodologies Investigate and root cause issues found during the IP development stage WHO WE ARE LOOKING FOR: 3rd/4th year Computer Engineering or Computer Science students with:
Understanding of digital design principles Understanding of Object Oriented Coding practices
Experience with Systemverilog, C or C++ programming languages
Experience with Python, Perl or other scripting languages is an asset Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.
An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to…
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