Physical Design Engineer

ENTRY LEVEL - Bachelor's degree with up to 2 years experience or a recent Master's degree with no experience.

The Physical Design engineer will be responsible for executing end-to-end digital physical design activities—from RTL or netlist input through final GDSII—ensuring high-quality, high-performance, and manufacturable digital blocks and subsystems. The role requires strong expertise in synthesis, floorplanning, place & route (P R), timing closure, power integrity, extraction, verification, and tape-out preparation.

You will collaborate closely with digital/analog design and CAD/PDK teams, verification, and program management to deliver robust silicon on schedule.

Key Responsibilities

· Perform fully digital physical layout design including:
Floor planning, power planning, place and route, physical verification and sign-off flows, Extraction, STA, EM/IR analysis, and reliability checks.

· Perform logic synthesis meeting timing, area, and power targets, Debug and resolve timing violations through logic restructuring, Implement functional ECOs.

· Work closely with front-end RTL designers, analog/mixed-signal layout teams, and verification engineers to ensure seamless integration of digital components.

· Participate in floor planning reviews, physical sign-off reviews, and tape-out readiness assessments.

· Bachelor’s /Master’s degree in electrical and computer Engineering, or related field.

· 3+ years experience in ASIC digital physical design implementation (including internships and hands on practical academic assignments).

· Strong understanding of digital and analog IC fundamentals, standard-cell architecture, timing, power, and signal-integrity principles.

· Proficient in using EDA tools like:
Innovus, Synthesis tools, STA tools, Extraction and sign-off tools (Voltus, Quantus, Calibre, or similar).

· Custom analog layout experience is an asset.

· Excellent communication and collaboration abilities.

· Ability to work independently and manage multiple tasks in a fast-paced environment.