ASIC Digital Design, Senior Staff Engineer

Overview

We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:
You are a passionate and driven ASIC Digital Design engineer with a deep understanding of high-speed digital and mixed-signal interfaces. You thrive when collaborating with diverse, cross-functional teams and excel in fast-paced, technically challenging environments. Your expertise in RTL design and physical implementation enables you to create innovative solutions that push the boundaries of semiconductor technology. You have a proven track record of tackling complex technical problems, from architecture through to silicon debug, and you’re adept at translating high-level requirements into high-quality, production-ready RTL.

Your communication skills—both written and verbal—are exceptional, allowing you to clearly articulate technical concepts and collaborate effectively across global teams. You embrace learning and continuous improvement, eagerly adopting new tools and methodologies to optimize results. With 7-10 years of hands-on experience in ASIC design, you’re confident in your ability to lead technical efforts, mentor junior engineers, and contribute to the advancement of industry-leading memory IP.

You bring a positive, solutions-oriented mindset, and are motivated by the opportunity to make a tangible impact on next-generation computing and connectivity.

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using System Verilog and Verilog.
• Collaborating with cross-functional teams, including analog, mixed-signal, and physical design groups, to ensure seamless integration and optimal performance.
• Addressing challenging physical implementation requirements, and innovating solutions for timing closure, low power, and high-speed design.
• Creating clear and comprehensive specification documents, and providing technical guidance across multiple teams and global sites.
• Automating design and verification tasks using scripting languages to improve efficiency and reliability.
• Supporting the full ASIC and IP development flow, from concept through to silicon debug and production release.

• Drive the development of cutting-edge HBM PHY IP, enabling industry-leading memory bandwidth for next-generation computing systems.
• Enhance the performance, power efficiency, and reliability of digital and mixed-signal designs in advanced process technologies.
• Mentor and empower team members, fostering a culture of technical excellence and collaborative problem solving.
• Shape Synopsys’ leadership in the memory interface IP market by delivering robust, high-quality solutions adopted by top semiconductor companies worldwide.
• Contribute to the successful integration of complex IP into customer SoCs, accelerating time-to-market and product differentiation.
• Influence architectural and implementation decisions, ensuring Synopsys remains at the forefront of technology innovation.

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in System Verilog and Verilog for RTL development.
• Strong background in high-speed design, timing closure, and low power design techniques and strategies.
• Experience with the entire ASIC and IP development flow, including DFT/DFM, and debugging complex hardware issues.
• Proficiency in automating tasks using scripting languages (e.g., Python, Perl, TCL).
• Familiarity with modeling analog and mixed-signal circuits and understanding of physical implementation challenges.
• Ability to write clear, detailed specification documents and…