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Senior ASIC Design Engineer – Verilog​/PPA Expert

Job in Ottawa, Ontario, Canada
Listing for: Celero Communications, Inc.
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 150000 - 250000 CAD Yearly CAD 150000.00 250000.00 YEAR
Job Description & How to Apply Below
A semiconductor startup in Canada is seeking an ASIC Design Engineer to contribute to innovative optical transceiver development. You will design digital circuits, ensure performance optimizations, and collaborate with teams on integration tasks. Candidates should have a degree in Electrical Engineering and a minimum of 3 years in digital design, alongside proficiency in Verilog/System Verilog. An attractive salary package between $150,000 - $250,000 annually is offered based on experience and qualifications.
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Position Requirements
10+ Years work experience
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