Senior SoC Verification Lead - UVM, SystemVerilog, Remote

An established industry player is seeking a Senior SoC Design Verification Engineer to join their innovative team. In this remote role, you will leverage your extensive experience in functional verification of complex SoCs using UVM and System Verilog. Your contributions will include developing test plans, writing test benches, and collaborating with skilled engineers to ensure design integrity. This position offers a unique opportunity to lead projects and mentor junior team members while working in a dynamic environment that values creativity and technical excellence.

If you are passionate about advancing technology and want to make a significant impact, this role is for you.
#J-18808-Ljbffr