Chip Physical Design Lead

Position: Full Chip Physical Design Lead
Full Chip PD Lead (8+ Years Experience)
Locations:  Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, Pune

Job Description:

We are seeking a highly experienced  Full Chip PD Lead  to drive top-level physical design activities for complex, high-performance SoCs. The ideal candidate will have hands-on expertise in database integration, physical verification, and leading mid-sized engineering teams.

Key Responsibilities:

Lead  top-level database integration  and manage incremental updates for derivative chips, including  incremental pin alignment and routing
Own  block integration , including  analog IP integration , and ensure clean Physical Verification (PV) sign-off
Drive automation and improve flow efficiency using  Perl, Tcl, Awk, or Python
Provide technical guidance and leadership to a team of  5–8 engineers
Collaborate cross-functionally to ensure consistency between block-level and top-level deliveries
Requirements:
8+ years of experience in  Full Chip Physical Design
Proven experience working on chips with  GHz-range clocks  and  multi-million instance complexity
Hands-on experience designing advanced SoCs in  7nm and below technology nodes
Strong communication skills and ability to lead and mentor engineering teams

If you’re passionate about driving full-chip PD execution for advanced nodes and leading high-impact teams, we’d love to connect.