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Senior FPGA Verification Engineer; UVM, SystemVerilog

Job in Mountain View, Santa Clara County, California, 94039, USA
Listing for: Jobs via Dice
Full Time position
Listed on 2026-01-13
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Position: Senior FPGA Verification Engineer (UVM, SystemVerilog)
A recruiting platform is seeking an experienced FPGA Verification Engineer for a full-time position in Mountain View, CA. The role involves strong understanding of FPGA design principles, proficiency in System Verilog and UVM verification methodology, and experience with verification tools like Questa Sim. The ideal candidate has over 8 years of experience in FPGA and strong debugging skills. This is an on-site position with a focus on quality assurance.
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Position Requirements
10+ Years work experience
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