Design Verification Engineer

As a Design Verification Engineer at Tessolve, you will be part of the VLSI Design and Verification team working on verification of advanced ASIC/IP blocks and subsystem features. You’ll be responsible for building robust verification environments, executing feature-level and system-level tests, and ensuring design readiness for silicon tape-out and integration.

• Develop verification plans based on design specifications and requirements.
• Define verification scope, objectives, and coverage goals for IP/subsystem/SoC features.

• Architect and implement predictive UVM/System Verilog test benches.
• Build reusable verification components (scoreboards, monitors, drivers).
• Integrate Verification IP (VIPs) for complex protocol interfaces.

• Write directed and constrained-random test cases to validate functionality.
• Apply assertion-based verification (SVA) to capture functional checks.
• Run regressions and feature-driven scenarios for coverage closure.

• Analyze simulation failures using tools (e.g., Verdi, DVE).
• Debug design/testbench interactions and provide root‑cause analysis.

• Report and drive functional/code/line coverage to closure.
• Ensure thorough documentation and participate in verification reviews.
• Work closely with RTL design, DFT, STA, and firmware teams to align verification goals.
• Participate in Integration and Silicon Bring‑up readiness activities.

• Bachelor’s / Master’s in Electrical/Electronics/Computer Engineering or related field.
• 6+ years hands‑on experience in ASIC/IP Design Verification or related DV roles.
• Proficiency with System Verilog and UVM methodologies.
• Experience with simulation & verification tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Strong debugging skills, waveform analysis, and issue reporting.
• Good scripting skills (Python, Perl, TCL, Shell) for automation and regressions.
• Solid understanding of SoC architecture and digital interfaces.

• Experience with high‑speed interfaces (e.g., PCIe, USB, DDR/LPDDR, Ethernet, CXL).
• Familiarity with coverage‑driven verification and metric analysis.
• Exposure to formal verification, low‑power verification (UPF/CPF), or emulation.
• Knowledge of DFT concepts and collaboration with test teams.
• Experience working in multi‑national teams with global delivery models.

• Opportunity to work on cutting‑edge semiconductor designs in a global engineering team.
• Hands‑on experience across the pre‑silicon verification lifecycle from plan to sign‑off.
• Exposure to advanced methodologies and tools used in modern DV flows.