Senior ASIC Verification Engineer; UVM/SystemVerilog
Job in
California, Moniteau County, Missouri, 65018, USA
Listed on 2026-03-01
Listing for:
Tessolve
Full Time
position Listed on 2026-03-01
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer, Engineering Design & Technologists, Test Engineer
Job Description & How to Apply Below
Location: California
A semiconductor engineering firm in California is seeking an experienced Design Verification Engineer to join their VLSI Design and Verification team. You will be responsible for building robust verification environments, defining verification plans, and ensuring design readiness for silicon tape-out. Ideal candidates will have a Master's degree in Electrical Engineering and over 6 years of experience in ASIC design verification, along with proficiency in System Verilog and UVM methodologies.
This position offers a chance to work on cutting-edge semiconductor designs in a collaborative global team environment.
#J-18808-Ljbffr
Position Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×