Distinguished Engineer, Digital ASIC
Listed on 2026-02-28
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Engineering
Software Engineer, Systems Engineer, Hardware Engineer, Electronics Engineer
We’re a team of bold thinkers, problem-solvers, and innovators driving a digital revolution in medical imaging.
Let’s build something extraordinary together!
Innovation is what we do. Our values are how we make it happen. They shape our work, our culture, and the impact we create.
Our team values focus, dedication, innovation, and the power of what can happen when they converge.Benefits of working lth and wellness
Coverage starts on day one, with options for all partners and children. Butterfly provides 100% coverage for medical, dental, and vision through our Base Plan, and offers flexible Buy-Up Plans with employee contributions. We also fund your HSA annually for out-of-pocket expenses and offer other pre‑tax savings like the Dependent Care Account (DCA). For added peace of mind, Butterfly includes life insurance and disability coverage for you and your family during unexpected events.
Retirementsavings
Save for your retirement utilizing pre‑tax or post‑tax 401(k) contributions, with a company match that vests immediately!
Parental leaveIf you’re a soon-to-be parent, we aim to provide you with time to bond with your growing family, along with additional support as you transition back to work. We also offer support for employees during pregnancy loss.
Flexible paid time offWe offer Flexible (reasonable) PTO to help you rest and reset, along with 10 U.S. holidays observed each year. Additionally, we encourage employees to celebrate their birthday with Birthday PTO.
Flexible hybrid workAt Butterfly, we offer a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable work spaces, stocked kitchens, and opportunities to connect with peers.
Company DescriptionAt Butterfly Network, we’re leading a digital revolution in medical imaging, transforming an industry that has long relied on bulky, analog systems. With our proprietary Ultrasound-on-Chip™ technology, we’re democratizing healthcare by shifting ultrasound from the expensive, stationary systems of the past to the connected, mobile, and software-enabled platforms of today. In 2018, we launched the world’s first handheld, whole-body ultrasound, Butterfly iQ – followed by iQ+ in 2020 and iQ3 in 2024, each more powerful than the last.
Our innovation doesn’t stop terfly combines our advanced device with intelligent software, AI, services, and education to drive adoption of affordable, accessible imaging. Our technology is proving to help clinicians, clinics, and hospitals enhance care, cut costs, and expand imaging access. We’ve been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions, Fast Company’s World Changing Ideas, among other awards.
We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together!
Qualifications- BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience.
- 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands‑on RTL ownership.
- Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power‑aware design, and PPA (power, performance, area) tradeoffs.
- Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design.
- Strong RTL skills in System Verilog/Verilog to implement silicon‑proven digital architectures, including pipelined datapaths, control logic, state machines, and high‑throughput streaming interfaces.
- Experience architecting sustained high‑throughput digital datapaths, including buffering, arbitration, back pressure, bandwidth budgeting, and SRAM/memory hierarchy design.
- Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third‑party IP.
- Experience collaborating with verification teams to validate complex digital architectures and…
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