FPGA Architect
Listed on 2026-02-21
-
Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer
Job Title:
FPGA Architect
Location:
Rijswijk, Netherlands
Type:
Permanent
Brief:
We are seeking a seasoned FPGA Architect with a minimum of 10 years of experience to lead the design and development of FPGA-based platforms that support internal testing and validation of our precision, high-performance MEMS timing products. This role is critical to developing robust infrastructure for frequency measurement, low phase noise and low jitter characterization, production, and system-level validation
Responsibilities:
Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing
Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams
Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains
Own the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing closure, and bring-up
Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure
Champion design reviews, documentation standards, and continuous improvement practices
Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs
Requirements:
MS in Electrical Engineering, Computer Engineering, or related field
10+ years of hands-on experience in FPGA architecture and development (Xilinx, Intel/Altera, or similar)
Deep expertise in Verilog/VHDL, simulation tools (Model Sim, Vivado, etc.), and scripting (Python, TCL)
Proven track record in designing systems with low jitter, low phase noise, and high signal fidelity
Strong understanding of timing analysis, clock domain crossing, and high-speed interfaces (PCIe, DDR, SERDES)
Experience with lab bring-up, debugging tools (logic analyzers, oscilloscopes), and test automation
If this sounds of interest, please apply here or reach out to
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