Substrate​/Advanced Package Engineer

Overview

We are seeking a highly skilled and motivated Substrate / Advanced Package Engineer to join our cutting-edge 3

DIC design team. The ideal candidate will have a strong foundation in semiconductor physics, mechanical engineering principles, and EDA (Electronic Design Automation) tools, with a passion for innovation in advanced package design. The role involves design, simulation, and modeling of complex substrate and packaging technologies to support next generation 3

DIC applications.

• Design, simulate, and optimize advanced packaging for 3
  
  DIC applications.
• Collaborate with cross-functional teams to define specifications and requirements.
• Perform modeling of warpage, stress, reliability, and thermal performance using industry-standard EDA tools.
• Formulate and solve problems in research-driven, often ambiguous domains.
• Provide guidance on high-speed I/O modeling and integration.
• Develop and maintain documentation, including specifications, test plans, and design reviews. Stay current with industry trends, tools, and technologies in advanced packaging.

• Master’s degree or Ph.D. in Electrical Engineering, Mechanical Engineering, or a related field.
• 15+ years of hands-on expertise in advanced packaging technologies and substrate design.
• Understanding of semiconductor device physics and packaging process technologies.
• Strong knowledge of warpage, stress, and thermal effects in packaging.
• Proven ability to drive solutions in ambiguous, research-oriented contexts.
• Excellent problem-solving, analytical, and communication skills.
• Strong collaboration skills, with the ability to mentor junior engineers.
• Ability to balance strategic insight with hands-on technical execution.

• Experience with reliability, IR/EM, and multi-physics analysis.
• Familiarity with machine learning techniques for design optimization.
• Patents, publications, or demonstrated innovation in substrate or packaging domains.

• Ability to provide impactful, data-driven suggestions that influence design direction.
• Effective use of modeling and simulation to validate proposals.
• Establishing trust and credibility with global teams.
• Enabling adoption of new technologies within the 3
  
  DIC ecosystem.

• Primary work location is in Hsinchu or San Jose (Hsinchu preferred).
• Visa sponsorship may be considered for exceptional candidates.

At TSMC, you will be part of the world’s leading semiconductor foundry, driving cutting-edge innovation in advanced packaging and 3

DIC technologies. You will collaborate with world-class engineers, work on industry-defining projects, and shape the future of system integration. We offer unparalleled opportunities for growth, impact, and contribution to the global technology ecosystem.

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to…