Foundry Interface Engineer Bay Area, CA,

Proto is accelerating the world’s transition to an open economy with products that increase access and independence for everyone. We’re building Bitkey, a simple and safe self‑custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We’re developing these products in the open – you can read more about them ld and mining.build

. Within Proto, our Bitcoin Products team delivers the product and go‑to‑market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us!

The Foundry Interface Engineer will engage with Foundry partners/third‑party vendors as well as internal teams to continuously improve the design of our ASICs. This work will include partnering with OSAT to continuously monitor and review production wafer test data, and work with standard cell level circuit designers to analyze the results. Based on the analysis the engineer will make requests to the foundry for process fine tuning.

• Engage with Foundry partners/third‑party vendors to manage foundry PDK/DK and design library collaterals
• Guide internal IP/design teams on appropriate usage of technology attributes/offerings in accordance with product requirements (e.g., performance, power, area, and cost).
• Collaborate with internal third‑party infrastructure, customization, test‑chip, methodology, and packaging and product test engineering teams for seamless execution of product bring‑up and productization.
• Review and assess Foundry silicon data against SPICE/design goals and compile SPICE to Silicon gap analysis. Drive foundry partners on CIPs to improve foundry process to meet technology entitlement and product goals.
• Work with foundry to identify potential device parameter changes to enable efficient low‑voltage operation
• Work closely with circuit designers to determine what device improvements could improve circuit performance and energy efficiency
• Work with test engineers to analyze and validate production wafer data
• Contribute to binning strategy to maximize parametric yield

• 10+ years of post‑education experience in FAB/Fabless environments, technology definition and bring‑up, device/process architecture, and NPI
• Experience with foundry design kit, SPICE, DR/DRC evaluation, SPICE to Si assessment
• Experience with advanced node device physics (e.g., FinFET/GAA), backside power, product design phases
• Experience with product KPIs, DTCO, and parametric, DLY/PLY analysis/gap closure
• Understanding of low power design techniques (e.g., Vmin reduction, power gating, multi‑voltage design, chip power, clock network and optimization)
• Understanding of layout effects and impact to circuit design
• Excellent statistical, data analysis, and communication skills

• Master’s degree or PhD in Electrical Engineering, Physics, or other related Engineering field with emphasis on semiconductor materials/devices and device physics (not a substitute for professional experience)
• Familiar with advanced FinFET technology nodes (3nm and 2nm)
• Familiar with PDK and device models
• Previous work experience at semiconductor foundries
• Familiar with standard cell design and layout

Block is an equal opportunity employer evaluating all employees and job applicants without regard to identity or any legally protected class. We will consider qualified applicants with arrest or conviction records for employment in accordance with state and local laws and “fair chance” ordinances.